Alif Semiconductor /AE722F80F55D5LS_CM55_HE_View /LPI2S /I2S_RXFFR

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Interpret as I2S_RXFFR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)RXFFR

RXFFR=Val_0x0

Description

Receiver Block FIFO Reset Register

Fields

RXFFR

Receiver FIFO Reset. Writing a 0x1 to this bit flushes all the RX FIFOs (this is a self clearing bit). The Receiver block must be disabled before writing to this bit.

0 (Val_0x0): Does not flush the RX FIFO

1 (Val_0x1): Flushes the RX FIFO

Links

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